ADCCCN Maxim Integrated Analog to Digital Converters – ADC CMOS High -Speed 8-Bit A/D Converter with Track/Hold Function datasheet, inventory. ADCCCN/NOPB Texas Instruments Analog to Digital Converters – ADC 8B Hi Spd Compatible A/D Cnvtr datasheet, inventory, & pricing. For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at. , or visit Maxim’s website at

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In the ADC, one bank of 15 comparators is used in each.

INT going low indicates that the. If an interrupt driven. When WR is returned high.

ADCCCN Datasheet(PDF) – National Semiconductor (TI)

MS means most significant. Connection and Functional Diagrams. The MS most signifi. For ease of interface to microprocessors, the ADC has.

Switch leakage and inverter bias current. Though V IN is not itself differential, the reference design. In this configuration, a complete conversion is done.


When mode is low. Figure 11 also outlines how the converter’s interface timing. V20A — Molded Chip Carrier.

ADC0820 CMOS High-Speed 8-Bit A/D Converter With Track/Hold Function

When mode is high. Sampled-data comparators, by nature of their input switch. By using a half-flash conversion technique, the 8-bit. The ADC has two basic interface modes which are.

V OUT 0Logical “0”. Z switches are closed in the zeroing cycle. These two sets of comparators operate.

The input capacitors must charge to the input voltage. INT and can exercise a read after only ns Figure 9. LS means least significant. Figures 2, 3, 4. Overflow output — If the analog input is.

The equivalent input circuit of the ADC is shown in. By adding a second capacitor and another set of. Absolute Maximum Ratings Notes 1, 2. A comparison requires two cycles, one for zeroing the com. In datasheft, about 12 pF of input stray capacitance.

ADC Technical Data

Driven by the 4. All voltages are measured with respect to the GND pin, unless otherwise specified.


Logic Input Threshold Voltage vs. The input capacitor now subtracts its stored voltage. Each flash ADC is made. As R S increases, it will take longer for the input. ESD Susceptability Note 9. I IN 0Logical “0”. The DAC output is actually the tap on the resistor ladder. CS must be low in order for the RD or.

This is accomplished by using the same resistor. The ADC, with no such. To take a full 8-bit. WR then RD Mode. Power Supply as Reference.